{"id":219,"date":"2015-07-22T00:10:08","date_gmt":"2015-07-22T00:10:08","guid":{"rendered":"http:\/\/www.kurzweilai.net\/?p=257121"},"modified":"2015-07-25T00:56:27","modified_gmt":"2015-07-25T00:56:27","slug":"korean-researchers-grow-wafer-scale-graphene-on-a-silicon-substrate","status":"publish","type":"post","link":"https:\/\/hoo.central12.com\/fugic\/2015\/07\/22\/korean-researchers-grow-wafer-scale-graphene-on-a-silicon-substrate\/","title":{"rendered":"Korean researchers grow wafer-scale graphene on a silicon substrate"},"content":{"rendered":"
\"\"<\/a>

Wafer-scale (4 inch in diameter) synthesis of multi-layer graphene using high-temperature carbon ion implantation on nickel\/SiO2\/silicon (credit: J.Kim\/Korea University, Korea)<\/p><\/div>\n

Taking graphene a step closer to realistic commercial applications in silicon microelectronics,\u00a0Korea University<\/a> researchers have developed a simple microelectronics-compatible method for growing multi-layer graphene on a high-quality, wafer-scale (four inches in diameter) silicon substrate.<\/p>\n

The method is based on the ion implantation technique — a process in which ions are accelerated under an electrical field and smashed into a semiconductor. The impacting ions change the physical, chemical, or electrical properties of the semiconductor.<\/p>\n

Because of its high conductivity, “graphene is a potential contact electrode and an interconnection material linking semiconductor devices to form the desired electrical circuits, explained Jihyun Kim<\/a>, the team leader and a professor in the Department of Chemical and Biological Engineering at Korea University.<\/p>\n

However, “to deposit large-area graphene that is free of wrinkles, tears, and residues on silicon wafers requires low temperatures. That can’t be achieved with conventional chemical vapor deposition, which requires a high growth temperature — above 1,000 degrees Celsius.” That can cause strains, metal spiking, cracks, wrinkles, and contaminants from diffusion of dopants.<\/p>\n

“Our synthesis method is controllable and scalable, allowing us to obtain graphene as large as the size of the silicon wafer,” Kim said. The researchers’ next step is to further lower the temperature in the synthesis process and to control the thickness of the graphene for manufacturing production.<\/p>\n

The research is described in an open-access paper<\/a> published this week in the\u00a0<\/em>journal\u00a0Applied Physics Letters.<\/em><\/p>\n

\n

Abstract of\u00a0Wafer-scale synthesis of multi-layer graphene by high-temperature carbon ion implantation<\/em><\/strong><\/p>\n

We report on the synthesis of wafer-scale (4\u2009in. in diameter) high-quality\u00a0multi-layer\u00a0graphene using high-temperature\u00a0carbon\u00a0ion implantation\u00a0on thin\u00a0Ni\u00a0films on a substrate of SiO2\/Si.Carbon\u00a0ions were bombarded at 20\u2009keV and a dose of 1\u2009\u00d7\u20091015\u2009<\/sup>cm\u22122<\/sup>\u00a0onto the surface of the Ni\/SiO2\/Si substrate at a\u00a0temperature\u00a0of 500\u2009\u00b0C. This was followed by high-temperature activation annealing (600\u2013900\u2009\u00b0C) to form a sp2<\/sup>-bonded honeycomb structure. The effects of post-implantation activation annealing conditions were systematically investigated by micro-Raman spectroscopy and\u00a0transmission electron microscopy.\u00a0Carbon\u00a0ion implantation\u00a0at elevated\u00a0temperatures\u00a0allowed a lower activation annealing\u00a0temperature\u00a0for fabricating large-area\u00a0graphene.\u00a0Our results indicate that carbon-ion\u00a0implantation\u00a0provides a facile and direct route for integrating\u00a0graphene\u00a0with Si microelectronics.<\/p>\n","protected":false},"excerpt":{"rendered":"

Taking graphene a step closer to realistic commercial applications in silicon microelectronics, Korea University researchers have developed a simple microelectronics-compatible method for growing multi-layer graphene on a high-quality, wafer-scale (four inches in diameter) silicon substrate. The method is based on the ion implantation technique — a process in which ions are accelerated under an electrical field […]<\/p>\n","protected":false},"author":13,"featured_media":0,"comment_status":"closed","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[48,43],"tags":[],"class_list":["post-219","post","type-post","status-publish","format-standard","hentry","category-electronics","category-news"],"_links":{"self":[{"href":"https:\/\/hoo.central12.com\/fugic\/wp-json\/wp\/v2\/posts\/219"}],"collection":[{"href":"https:\/\/hoo.central12.com\/fugic\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/hoo.central12.com\/fugic\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/hoo.central12.com\/fugic\/wp-json\/wp\/v2\/users\/13"}],"replies":[{"embeddable":true,"href":"https:\/\/hoo.central12.com\/fugic\/wp-json\/wp\/v2\/comments?post=219"}],"version-history":[{"count":1,"href":"https:\/\/hoo.central12.com\/fugic\/wp-json\/wp\/v2\/posts\/219\/revisions"}],"predecessor-version":[{"id":220,"href":"https:\/\/hoo.central12.com\/fugic\/wp-json\/wp\/v2\/posts\/219\/revisions\/220"}],"wp:attachment":[{"href":"https:\/\/hoo.central12.com\/fugic\/wp-json\/wp\/v2\/media?parent=219"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/hoo.central12.com\/fugic\/wp-json\/wp\/v2\/categories?post=219"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/hoo.central12.com\/fugic\/wp-json\/wp\/v2\/tags?post=219"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}